1. Technical Field
The invention relates to a semiconductor device and, more particularly, to an impedance controller for impedance matching with an external device.
2. Discussion of the Related Art
A variety of semiconductor devices, such as microcomputers, memory devices and the like, are used to construct a variety of electrical products. In most cases, the semiconductor devices have input/output pins for receiving and transmitting external data, an output circuit for providing internal data to external devices, and the like. A semiconductor device may provide internal data to other semiconductor devices using a transmission line. In this case, the output impedance of the input/output pins and the impedance of the transmission line must be matched to optimize signal transmission.
One method for realizing impedance matching is to design a system with output impedance matching transmission line impedance and terminating an input to minimize reflective waves. In this method, however, an impedance difference arises due to temperature variations, process changes, and other operating environment characteristics that differ from the design environment. A need exists, therefore, for a device that provides constant impedance regardless of environmental changes. For this reason, some have devised a programmable impedance controller (PIC) capable of sensing transmission line characteristic impedance and providing relevant information to the output circuit. The PIC performs impedance matching according to an external resistor resistance when the resistor is connected to the system by a user. In addition, the controller matches internal to external impedance by actively updating a digital code in a certain period relative to environmental changes, e.g., changes in voltage and temperature.
One example of a conventional PIC is disclosed in U.S. Pat. No. 6,573,746 to Nam-Seog Kim et al. The '746 patent claims priority to Korean Patent No. 10-0394586 entitled Impedance Control Circuit, both the '746 patent and the Korean '586 patent are assigned to Samsung Electronic Co., Ltd.
FIG. 1 is a block diagram of a PIC. Referring to FIG. 1, the PIC includes a current mirror section CUR for converting an external impedance RQ connected through a pad ZQ PAD (e.g., a chip pad), to a current I. Up and down detectors UPDET 16 and DNDET 15 include a transistor array that is programmed to have the same up and down impedance as the external impedance RQ. Up and down selectors UPSEL 18 and DNSEL 17 compare outputs from the detectors 15 and 16 to a reference voltage to control outputs of counters 12 and 14. The counters 12 and 14 generate digital impedance codes. A register IMPREG 20 stores the impedance codes and a code transmitter TRANS 21 serially transmits the impedance codes.
The PIC operates as follows. The current mirror section converts the external impedance RQ, connected with the pad ZQ PAD, to the current I as follows. The comparator 10, which is a component of the current mirror section CUR, compares a node voltage VZQ at the pad ZQ PAD to a reference voltage VREF to control a gate voltage of a PMOS transistor M0. If the node voltage VZQ is larger than the reference voltage VREF, the output from the comparator 10 increases, and in turn, an amount of a current flowing through the PMOS transistor M0 decreases. Since all the current flowing through the PMOS transistor M0 flows through the external impedance RQ, the node voltage VZQ will lower below a previous value. On the contrary, if the node voltage VZQ is smaller than the reference voltage VREF, the output of the comparator 10 decreases and, in turn, the amount of the current flowing through the PMOS transistor M0 increases. Since all the current flowing through the PMOS transistor M0 flows through the external impedance RQ, the node voltage VZQ will increase over the previous value. Through this process, the gate voltage of the PMOS transistor is controlled so that the node voltage VZQ has a value of VDDQ/2. At this time, the current I flowing through the PMOS transistor becomes VDDQ/2RQ.
The current I is also supplied to the up and down detectors 15 and 16 via the current mirror. The current I is duplicated and delivered to the down detector 15 by a PMOS transistor M3. Further, the same current I is duplicated and delivered to the up detector 16 by a PMOS transistor M1, a NMOS transistor M2, and a NMOS transistor M4.
A bias condition of the up and down detectors must be the same as the external impedance RQ so that the up and down detectors 15 and 16 have the same impedance as the external impedance RQ. In other words, when the up and down detectors 15 and 16 have output voltages UCUR and DCUR at VDDQ/2 and the current at VDDQ/2RQ, the up and down detectors 15 and 16 would have the same impedance as the external impedance RQ.
The comparators 11 and 13 compare the output voltage UCUR and DCUR from the up and down detectors 15 and 16 with the reference voltage VREF, e.g., VDDQ/2, to determine whether to increase or decrease the size of a transistor array that constitute the up and down detectors 15 and 16.
The outputs from the comparators 11 and 13 are delivered to first and second counters 12 and 14. The counters 12 and 14 generate impedance codes to program the up and down detectors 15 and 16.
The impedance codes outputted from the counters 12 and 14 are also sent to the up and down detectors 15 and 16 to control the size of the transistor array.
Thereafter, the output voltages UCUR and DCUR from the up and down detectors 15 and 16 are compared back to the reference voltage VREF by the comparators 11 and 13. This comparison result is sent to the counters 12 and 14.
The above-described impedance controller makes the output voltages UCUR and DCUR from up and down detectors 15 and 16 be VDDQ/2 through such series of processes so that the impedance of the up and down detectors 15 and 16 is the same as the external impedance RQ.
The selectors 17 and 18 serve to detect a dithering phenomenon and store the same impedance code as the external impedance RQ in the register 20. The dithering phenomenon may indicate when the output voltages UCUR and DCUR output from the detectors 15 and 16, respectively, are not exactly obtained as VDDQ/2 but have an amplitude with a quantization error. The quantization error may be based on the oscillating voltage VDDQ/2. The dithering phenomenon implies that since the impedance of the up and down detectors in the impedance controller is made as two values most similar to the external impedance RQ, the values must be detected to select an optimal one of two impedance codes.
The impedance codes stored in the register 20 by the selectors 17 and 18 are transmitted by the code transmitter 21, thus adjusting the output impedance.
FIGS. 2 and 3 illustrate graphs showing impedance codes and impedance resolution for different external impedances in the impedance controller of FIG. 1.
FIG. 2 illustrates a graph of impedance codes according to impedance values, where an X axis denotes an impedance code and a Y axis denotes an impedance value. FIG. 2 demonstrates that when the external impedance is DDR1 (50Ω) and DDR3 (25Ω), an impedance code (i.e., 20) at the impedance value, DDR3 (25Ω), is larger than an impedance code (i.e., 10) at DDR1 (50Ω).
FIG. 3 illustrates a graph showing impedance codes and impedance resolution for respective external impedances, where an X axis denotes an impedance code and a Y axis denotes impedance resolution. It can be seen that when the external impedance is DDR1 (50Ω) and DDR3 (25Ω), the impedance resolutions dependent on the impedance code significantly differ as 40 and 30 at the impedance values, DDR3 (25%) and DDR1 (50%). In other words, if the controller is designed to meet both 50Ω and 25Ω, which correspond to DDR1 and DDR3, respectively, the DDR3 has impedance resolution of about 2% while the DDR1 has impedance resolution of about 4.4%.
Because a range of the impedance is determined by controlling the size of the transistor array that constitutes the detectors, the impedance resolution is high when the size of the transistor array is large and is low when the size of the transistor array is small. A problem arises that, when the impedance controller is applied to two systems having different external impedance, there exists a large difference in impedance resolution between the two systems. Another problem may be that the impedance code varies depending on change in processes, which affects the impedance resolution.
Accordingly a need remains for an improved impedance controller and an impedance control method.